Fin field effect transistors (FinFETs) and methods for making the same

ABSTRACT

In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.

The present application is a division of U.S. patent application Ser.No. 11/132,652 filed on May 19, 2005, which is incorporated by referenceherein in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly to fin field effect transistors (FinFETs) and methodsfor making the same.

BACKGROUND

A FinFET is a transistor that includes a fin (e.g., of silicon)separating a first gate from a second gate, which is opposite the firstgate, of the transistor. Yields of conventional methods of manufacturingFinFETs are reduced due to fin damage during manufacturing.Additionally, the ability to tailor the structure of FinFETs resultingfrom such conventional methods may be limited. For example, gatedielectrics respectively coupled to opposing sides of the fin duringmanufacturing are of the same width and formed of the same material.Further, a work function of a gate conductor coupled to the first gateis the same as a work function of a gate conductor coupled to the secondgate. Accordingly, improved FinFETs and methods for making the same aredesirable.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a first method is provided forsemiconductor device manufacturing. The first method includes the stepsof (1) forming a first side of a fin of a fin field effect transistor(FinFET); (2) processing the first side of the fin; and (3) forming asecond side of the fin while supporting the first side of the fin.

In a second aspect of the invention, a first apparatus is provided. Thefirst apparatus is a semiconductor device that includes (1) a fin,having a first side and a second side, adapted to define a channel ofthe semiconductor device; (2) a first dielectric of a first materialcoupled to the first side of the fin; and (3) a second dielectric of asecond material coupled to the second side of the fin.

In a third aspect of the invention, a second apparatus is provided. Thesecond apparatus is a semiconductor device that includes (1) a fin,having a first side and a second side, adapted to define a channel ofthe semiconductor device; (2) a first gate conductor of a first materialcoupled to the first side of the fin; and (3) a second gate conductor ofa second material coupled to the second side of the fin. The first andsecond gate conductors are adapted to control a current through thechannel.

In a fourth aspect of the invention, a third apparatus is provided. Thethird apparatus is a semiconductor device that includes (1) a fin,having a first side and a second side, adapted to define a channel ofthe semiconductor device; (2) a first dielectric of a first widthcoupled to the first side of the fin; and (3) a second dielectric of asecond width coupled to the second side of the fin. Numerous otheraspects are provided in accordance with these and other aspects of theinvention.

Other features and aspects of the present invention will become morefully apparent from the following detailed description, the appendedclaims and the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a cross-sectional front view of a step of a firstexemplary method of forming a FinFET in which nitride is formed on asubstrate in accordance with an embodiment of the present invention.

FIGS. 2A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide regions are formed in the substrate inaccordance with an embodiment of the present invention.

FIGS. 3A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which nitride is etched in accordance with anembodiment of the present invention.

FIGS. 4A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which an oxide is deposited on the substrate inaccordance with an embodiment of the present invention.

FIGS. 5A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide spacers are formed in accordance with anembodiment of the present invention.

FIGS. 6A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a mask is formed on the substrate inaccordance with an embodiment of the present invention.

FIGS. 7A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 8A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 9A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a first gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.

FIGS. 10A-C illustrate respective top, cross front and cross-sectionalside views of a step of the first exemplary method of forming a FinFETin which a first gate conductor is formed on the substrate and an oxidelayer is formed on the gate conductor in accordance with an embodimentof the present invention.

FIGS. 11A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 12A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 13A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a second gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.

FIGS. 14A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a second gate conductor is formed on thesubstrate and planarized in accordance with an embodiment of the presentinvention.

FIGS. 15A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which portions of the gate conductors and gatedielectrics are etched from the substrate in accordance with anembodiment of the present invention.

FIGS. 16A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which an insulator is deposited on the substrate inaccordance with an embodiment of the present invention.

FIGS. 17A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which wiring is formed on a transistor formed in thesubstrate in accordance with an embodiment of the present invention.

FIG. 18 illustrates a cross-sectional front view of a step of a secondexemplary method of forming a FinFET in which nitride is formed on asubstrate in accordance with an embodiment of the present invention.

FIGS. 19A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 20A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 21A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a first gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.

FIGS. 22A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a first gate conductor is formed on thesubstrate and an oxide layer is formed on the gate conductor inaccordance with an embodiment of the present invention.

FIGS. 23A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide regions are formed in the nitride of thesubstrate in accordance with an embodiment of the present invention.

FIGS. 24A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 25A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide spacers are formed on the substrate inaccordance with an embodiment of the present invention.

FIGS. 26A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention.

FIGS. 27A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a second gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.

FIGS. 28A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a second gate conductor is formed on thesubstrate and planarized in accordance with an embodiment of the presentinvention.

FIGS. 29A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide and the second gate conductor areplanarized in accordance with an embodiment of the present invention.

FIGS. 30A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide above a fin is etched from the substratein accordance with an embodiment of the present invention.

FIGS. 31A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a fin and portions of the first and secondgate conductors are etched from the substrate in accordance with anembodiment of the present invention.

FIGS. 32A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which portions of the gate dielectrics are etchedfrom the substrate in accordance with an embodiment of the presentinvention.

FIGS. 33A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which an insulator is deposited on the substrate inaccordance with an embodiment of the present invention.

FIGS. 34A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which wiring is formed on a transistor formed in thesubstrate in accordance with an embodiment of the present invention.

FIG. 35 illustrates a simulated relationship between drain current andvoltages of first and second gates of a FinFET manufactured inaccordance with an embodiment of the present invention.

FIG. 36 illustrates first exemplary contours of constant electronconcentration in a plane cut through the channel of a FinFETmanufactured in accordance with an embodiment of the present invention.

FIG. 37 illustrates second exemplary contours of constant electronconcentration in the plane cut through the channel of the FinFET of FIG.36 in accordance with an embodiment of the present invention.

FIG. 38 illustrates a layout of conventional MOSFETs on a substrate toform NOR logic.

FIG. 39 illustrates a layout of FinFETs on a substrate to form NOR logicin accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention provides improved semiconductor devices andmethods for making the same. More specifically, the present inventionprovides improved fin field effect transistors (FinFETS) and methods formaking the same. The present methods of manufacturing FinFETs providesupport (e.g., on one or more sides) to silicon which ultimately forms afin during (e.g., throughout) manufacturing. In this manner, damage tothe fin while manufacturing a FinFET may be reduced and/or eliminated,and therefore, a semiconductor device manufacturing yield may beimproved.

Further, in contrast to conventional methods, the variability of astructure of a FinFET resulting from the present methods is not limited.For example, a FinFET in accordance with the present methods andapparatus may include a first gate conductor, which has a first workfunction, coupled to a first gate of the FinFET, and may include asecond gate conductor, which has a different (e.g., a second) workfunction, coupled to a second gate of the FinFET. Additionally oralternatively, a FinFET in accordance with the present methods andapparatus may include a first gate dielectric of a first materialcoupled to a first side of a fin of the FinFET and may include a secondgate dielectric of a different (e.g., second) material coupled to asecond side of the fin. Additionally or alternatively, a FinFET inaccordance with the present methods and apparatus may include a firstgate dielectric of a first width coupled to a first side of a fin of theFinFET and a second gate dielectric of a different (e.g., second) widthcoupled to a second side of the fin. In this manner, the present methodsand apparatus may overcome limitations of conventional semiconductordevice manufacturing methods and apparatus.

FIGS. 1-17C illustrate a first exemplary method of forming a FinFET inaccordance with an embodiment of the present invention and FIGS. 18-34Cillustrate a second exemplary method of forming a FinFET in accordancewith an embodiment of the present invention. In FIGS. 2A to 17A,cross-sectional front views are taken along cut lines 2B-2B to 17B-17B,respectively, and cross-sectional side views are taken along cut lines2C-2C to 17C-17C, respectively. Similarly, in FIGS. 19A to 34A,cross-sectional front views are taken along cut lines 19B-19B to34B-34B, respectively, and cross-sectional side views are taken alongcut lines 19C-19C to 34C-34C, respectively. FIG. 1 illustrates across-sectional front view of a step of a first exemplary method offorming a FinFET in which nitride is formed on a substrate in accordancewith an embodiment of the present invention. With reference to FIG. 1,the first exemplary method may process a silicon-on-oxide (SOI)substrate 100. The SOI substrate 100 may include a layer 102 of silicon(e.g., SOI layer) formed on oxide, thereby resulting in a buried oxide(BOX) layer 104. For example, during the first exemplary method, a layer106 of nitride (e.g., pad nitride) such as Si₃N₄ or the like may beformed on the substrate 100. Chemical vapor deposition (CVD) or anothersuitable method may be employed to form the nitride layer 106. Thethickness of the nitride layer may be about 10 nm to about 500 nm(although a larger or smaller thickness may be employed).

Alternatively, in some embodiments, a thin layer of oxide (e.g., padoxide) (not shown) may be formed on the SOI layer 102, and a layer ofpad nitride may be formed as described above on the pad oxide layer. Thepad oxide layer may be about 1 nm to about 20 nm thick (although alarger or smaller thickness may be employed).

FIGS. 2A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide regions are formed in the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 2A-C, the oxide regions 200-204 may be formed by patterningopenings onto the nitride layer 106 using a patterning technique such asphotolithography using photoresist and appropriate masking. Portions ofthe nitride layer 106 exposed through use of a mask employed during thepatterning technique may be etched selective to silicon. Therefore, theetching of nitride in the nitride layer 106 may stop at the silicon ofthe SOI layer 102.

Oxide (e.g., SiO₂) may be deposited on the substrate 100 using CVD oranother suitable deposition method such that the oxide is deposited inthe regions etched in the nitride layer 106. Thereafter, CMP or anothersuitable technique may be employed to planarize a top surface of thesubstrate 100 to the nitride layer 106. In this manner, one or moreoxide regions 200-204 may be formed. The one or more oxide regions200-204 may define regions for subsequently formed pads (e.g., contactpads) to contact a source or drain diffusion region of the substrate100. For example, a first and second oxide regions 200, 202 may defineregions for subsequently formed pads to contact first and second draindiffusion regions (e.g., silicon regions beneath the first and secondoxide regions 200, 202), respectively, of the substrate 100. Similarly,a third oxide region 204 may define a subsequently form pad to contact asource diffusion region (e.g., a silicon region beneath the third oxideregion 204) of the substrate 100.

FIGS. 3A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which nitride is etched in accordance with anembodiment of the present invention. With reference to FIGS. 3A-C, anopening may be patterned onto the nitride layer 106 using a patterningtechnique such as photolithography using photoresist and appropriatemasking. For example, portions of the nitride layer 106 may be exposedthrough use of a mask employed during the patterning technique.Thereafter, reactive ion etching (RIE) or another suitable method may beemployed to etch exposed portions of the nitride layer 106 selective tooxide and silicon. For example, the etching may remove nitride but maynot remove oxide and silicon. Therefore, the etching may remove portionsof the nitride layer 106 exposed by the opening, stopping at the SOIlayer 102. In this manner, a rectangular or polygonal region 300 may beformed in the nitride layer 106. A perimeter of the rectangular orpolygonal region 300 may determine, in part, a location of one or morefins that are subsequently formed during the first exemplary method.

FIGS. 4A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which an oxide is deposited on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 4A-C, CVD or another suitable deposition technique may beemployed to deposit (e.g., conformally) a layer 400 of oxide over a topsurface of the substrate 100. In this manner, a layer 400 of oxide mayform on exposed portions of a top surface 402 of the nitride layer,exposed portions of a top surface 404 of the oxide regions (200-204 inFIG. 2A), exposed portions of a top surface 406 of the SOI layer 102,and/or exposed sidewalls 408 of the nitride layer 106 that form therectangular or polygonal region (300 in FIGS. 3B-C). The thickness ofthe deposited layer 400 of oxide may determine a width of one or morefins that are subsequently formed. In one embodiment, the thickness ofthe deposited layer 400 of oxide may be about 2 nm to about 50 nm thick.However, a larger or smaller thickness may be employed. It should benoted from the cross-sectional front views, that the first exemplarymethod may form two FinFETs in the substrate 100 (e.g., a first FinFETon the left side of the front views and a second FinFET on the rightside of the front views). For ease of description, when convenient, onlythe FinFET manufactured on the left side of the cross-sectional frontviews may be referenced.

FIGS. 5A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide spacers are formed in accordance with anembodiment of the present invention. With reference to FIGS. 5A-C, RIEor another suitable etching method may be employed to etch portions ofthe oxide layer (400 in FIGS. 4A-C) selective to nitride. For example,portions of the oxide layer 400 deposited on the top surface 402 of thenitride layer 106, top surface 406 of the SOI layer 102 and/or topsurface 404 of the oxide regions 202-204 may be removed. In this manner,narrow oxide spacers 500 may be formed on sidewalls (e.g., verticalsidewalls) 408 of the nitride layer 106. The width of the narrow oxidespacers 500 may be the same as the thickness of the deposited layer 400of oxide.

FIGS. 6A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a mask is formed on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 6A-C, a mask (e.g., a fin cut or trim mask) 600 may bepatterned onto the substrate 100 using a patterning technique such asphotolithography using photoresist and appropriate masking, such that aportion 602 of an oxide spacer 500 may be exposed.

FIGS. 7A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which oxide is etched from the substrate inaccordance with an embodiment of the present invention. Morespecifically, with reference to FIGS. 7A-C, isotropic etching or anothersuitable method may be employed to remove the exposed portion (602 inFIGS. 6A and 6C) of the oxide spacer (500 in FIG. 6C). In this manner,the oxide spacer 500 may be selectively etched. Consequently, theportion of a top surface 700 of the SOI layer 102 previously covered bythe removed oxide spacer 500 is now exposed.

FIGS. 8A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 8A-C, RIE or another suitable method may be employed to etchthe exposed top surface (700 in FIGS. 7A-C) of the SOI layer 102selective to nitride and oxide. In this manner, the exposed top surface700 of the SOI layer 102 may be removed without removing the nitridelayer 106, the oxide regions 200-204, remaining portions of the oxidespacer 500 and/or the buried oxide (BOX) layer 104. Consequently, one ormore sidewalls 800 of the SOI layer 102 may be exposed. An exposedsidewall 800 may serve as a first side 802 of a subsequently formed fin(1200 in FIG. 12B) of the FinFET being manufactured. Therefore, gasphase doping, angled ion implantation or another suitable method fordoping a portion of silicon which may subsequently form a channel in theFinFET may be employed. Depending on the different types ofsemiconductor devices that are being manufactured, multiple maskingsteps may be employed during channel doping to provide desired dopingeffects to the different device types. In some embodiments, channeldoping may be omitted. For example, in embodiments in which a FinFETwith an extremely narrow fin for fully depleted operation are beingmanufactured, channel doping may not be required.

FIGS. 9A-C illustrate respective top, cross front and cross-sectionalside views of a step of the first exemplary method of forming a FinFETin which a first gate dielectric is formed on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 9A-C, thermal oxidation, thermal nitridation and/or conformaldeposition, or another suitable method may be employed to form a firstdielectric 900 on the sidewall 800 of the SOI layer 102. A portion 902(shown in phantom) of the SOI layer 102 on which the first gatedielectric 900 is formed may subsequently be formed into a fin (1200 inFIG. 12B). In this manner, the first gate dielectric 900 may be formedon a first side of the fin. The first gate dielectric 900 may include atleast one of a silicon oxide, silicon oxynitride, silicon nitride andhigh-k dielectric (e.g., silicon-hafnium-oxynitride). However, the firstgate dielectric 900 may include a larger or smaller number of and/ordifferent gate insulator materials. The electrical thickness of thefirst gate dielectric 900 may be about 1 nm to about 6 nm (although alarger or smaller thickness may be employed). It should be noted thatwhile the first side of the fin is formed an ultimate second side of thefin is included in the SOI layer 102 and supported thereby.

FIGS. 10A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a first gate conductor is formed on thesubstrate and an oxide layer is formed on the gate conductor inaccordance with an embodiment of the present invention. With referenceto FIGS. 10A-C, CVD or another suitable method may be employed todeposit a first gate conductor layer 1000 on a top surface of thesubstrate 100. Thereafter, CMP or another suitable method may beemployed to planarize the gate conductor layer 1000 to a top surface 402of the nitride layer 106. The first gate conductor may include at leastone of polysilicon (e.g., doped or undoped), a silicide (e.g., nickelsilicide or tungsten silicide) and/or a refractory material (e.g.,tungsten). However, the first gate conductor may include a larger orsmaller number of and/or different materials. The first gate conductormaterial may determine the work function of a first gate subsequentlycoupled thereto and a threshold voltage V_(t) associated with the firstgate.

RIE or another suitable method may be employed to recess the first gateconductor layer 1000 below a top surface 402 of the nitride layer 106.For example, the first gate conductor layer 1000 may be recessed about 5nm to about 50 nm below the top surface 402 of the nitride layer 106(although the first gate conductor layer 1000 may be recessed a largeror smaller distance). CVD or another suitable method may be employed todeposit a layer 1002 of oxide on a top surface of the substrate 100. CMPor another suitable method may be employed to planarize the oxide layer1002 to a top surface 402 of the nitride layer 106. In this manner, theoxide layer 1002 may serve as a protective cap for the first gateconductor layer 1000.

FIGS. 11A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 11A-C, RIE or another suitable method may be employed to etchnitride selective to oxide and silicon. In this manner, exposed portionsof the nitride layer (106 in FIGS. 10A-C) may be etched (e.g., down tothe SOI layer 102), and thereby removed from the substrate 100.

FIGS. 12A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 12A-C, RIE or another suitable method may be employed to etchsilicon selective to oxide. In this manner, exposed portions of the SOIlayer 102 may be etched (e.g., down to the BOX layer 104), and therebyremoved from the substrate 100. Consequently, a fin 1200 of the FinFETbeing manufactured may be formed. More specifically, the silicon etchingcauses one or more sidewalls 1202 of the SOI layer 102 to be exposed. Asidewall 1202 of the SOI layer exposed by the silicon etching may serveas a second side 1204 of the fin 1200. In this manner, the fin 1200 ofthe FinFET may be formed. The width of the fin 1200 may be defined bythe oxide spacer 500 overlying the fin 1200. It should be noted thatwhile the second side 1204 of the fin 1200 is formed, the front gateconductor layer 1000 and first dielectric layer 900 support the firstside 802 of the fin 1200.

FIGS. 13A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a second gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.With reference to FIGS. 13A-C, thermal oxidation, thermal nitridationand/or conformal deposition, or another suitable method may be employedto form a second dielectric 1300 on the sidewall 1202 of the SOI layer102. In this manner, the second gate dielectric 1300 may be formed onthe second side 1204 of the fin 1200. The second gate dielectric 1300may include at least one of a silicon oxide, silicon oxynitride, siliconnitride and high-k dielectric (e.g., silicon-hafnium-oxynitride).However, the second gate dielectric 1300 may include a larger or smallernumber of and/or different gate insulator materials. In someembodiments, the second gate dielectric material and/or width may bedifferent than the first gate dielectric material and/or width,respectively, (although the first and second gate dielectrics may be ofthe same material). The electrical thickness of the second gatedielectric 1300 may be about 1 nm to about 6 nm (although a larger orsmaller thickness may be employed). In some embodiments, the second gatedielectric material 1300 may be different than the first gate dielectricmaterial 900.

FIGS. 14A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which a second gate conductor is formed on thesubstrate and planarized in accordance with an embodiment of the presentinvention. With reference to FIGS. 14A-C, CVD or another suitable methodmay be employed to deposit a second gate conductor layer 1400 on a topsurface of the substrate 100. Thereafter, CMP or another suitable methodmay be employed to planarize the second gate conductor layer 1400 to atop surface of the oxide layers (e.g., the oxide regions 200-204 and theoxide layer (1002 in FIGS. 10A-C)). An over polish may be employed toremove portions of the second gate conductor layer 1400 atop the firstgate conductor layer 1000 and to remove the oxide layer (e.g., oxidecap) 1002 atop the first gate conductor layer 1000. Consequently, topportions of the oxide spacer 500 may be planarized.

The second gate conductor may include at least one of polysilicon (e.g.,doped or undoped), a silicide (e.g., nickel silicide or tungstensilicide) and/or a refractory material (e.g., tungsten). However, thesecond gate conductor may include a larger or smaller number of and/ordifferent materials. The second gate conductor material may determinethe work function of a second gate subsequently coupled thereto and athreshold voltage V_(t) associated with the second gate. In someembodiments, the second gate conductor material may be different thanthe first gate conductor material (although the first and second gateconductor materials may be the same).

FIGS. 15A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which portions of the gate conductors and gatedielectrics are etched from the substrate in accordance with anembodiment of the present invention. With reference to FIGS. 15A-C,photolithography using photoresist and appropriate masking or anothersuitable method may be employed to pattern the first and second gateconductor layers 1000, 1400 (e.g., selective to oxide). Consequently,portions of the first and second gate dielectrics 900, 1300 may beexposed. The exposed portions of the first and second gate dielectrics900, 1300 may be removed (e.g., stripped). Therefore, sidewalls of thesilicon beneath the oxide regions 200-204 may be exposed. Gas phasedoping, angled ion implantation or another suitable method for dopingsilicon beneath the one or more of the oxide regions 200-204, which maysubsequently form a source or drain diffusion region in the FinFET, maybe employed. In this manner, a source, drain or halo dopant may beintroduced to silicon beneath one or more of the oxide regions 200-204.Depending on the different types of semiconductor devices that are beingmanufactured, multiple masking steps may be employed during doping toprovide desired doping effects to the different device types. Duringdoping of the silicon beneath the oxide regions 200-204, the oxidespacer 500 overlying the fin 1200 (e.g., fin of silicon) which serves asa conducting channel may prevent the channel from becoming contaminated(e.g., by unwanted dopants).

FIGS. 16A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which an insulator is deposited on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 16A-C, CVD or another suitable method may be employed todeposit an insulator layer 1600, such as a planarizing glass (e.g.,phosphosilicate glass (PSG), borosilicate glass (BSG),borophosphosilicate glass (BPSG), etc.) on a top surface of thesubstrate 100. Thereafter, the insulator layer 1600 may be planarized.In some embodiments, the insulator may be reflowed to planarize theinsulator layer 1600. Alternatively, CMP or another suitable method maybe employed to planarize the insulator layer 1600. Further, in contrastto the glass described above, in some embodiments, a spin on dielectricor the like may be employed.

FIGS. 17A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the first exemplary method offorming a FinFET in which wiring is formed on a transistor formed in thesubstrate in accordance with an embodiment of the present invention.With reference to FIGS. 17A-C, masked anisotropic etching, such as RIE,or another suitable method may be employed to etch one or more contactvias 1700 through the insulator layer 1600 (e.g., to the first gateconductor layer 1000, second gate conductor layer 1400, a diffusionregion 1701 (e.g., silicon beneath an oxide region 200-204)).Thereafter, contacts 1702 may be formed. Further, metallurgy patterningor another suitable method may be employed to form wiring to one or moreof a first gate conductor contact, second gate conductor contact, asource diffusion region contact and/or a drain diffusion region contact.As stated, the first exemplary method may form two FinFETs in thesubstrate 100 (e.g., a first FinFET 1704 on the left side of thecross-sectional front view and a second FinFET 1706 on the right side ofthe cross-sectional front view). In some embodiments, a metal bridge1708 may be formed between gate conductors 1000, 1400 formed on opposingsides of the fin 1200 of the first FinFET 1704. In this manner, thefirst FinFET 1704 may operate with the same voltage applied to opposinggates (e.g., a first gate coupled to the first gate conductor 1000 and asecond gate coupled to the second gate conductor 1400) of the firstFinFET 1704 (e.g., similar to operation of a conventional FinFET). Incontrast, the wiring of the second FinFET 1706 may be such that opposinggates operate independently. In this manner the present methods andapparatus may provide a “split-gate” FinFET. However, the wiring for thefirst and/or second FinFET 1704, 1706 may be different. As describedabove, through use of the first exemplary method a FinFET in accordancewith an embodiment of the present invention may be formed.

FIGS. 18-34C illustrate a second exemplary method of forming a FinFET inaccordance with an embodiment of the present invention. With referenceto FIG. 18, similar to the first exemplary method, the second exemplarymethod may process a silicon-on-oxide (SOI) substrate 1800. The SOIsubstrate 1800 may include a layer 102 of silicon (SOI layer) formed onoxide, thereby resulting in a buried oxide (BOX) layer 104. For example,during the second exemplary method, a layer of nitride (e.g., padnitride) such as Si₃N₄ or the like may be formed on the substrate 1800.Chemical vapor deposition (CVD) or another suitable method may beemployed to form the nitride layer 106. The thickness of the nitridelayer 106 may be about 10 nm to about 500 nm (although a larger orsmaller thickness may be employed).

Alternatively, in some embodiments, a thin layer of oxide (e.g., padoxide) (not shown) may be formed on the SOI layer 102, and a layer ofpad nitride may be formed as described above on the pad oxide layer. Thepad oxide layer may be about 1 nm to about 20 nm thick (although alarger or smaller thickness may be employed).

FIGS. 19A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 19A-C, application and patterning of a photoresist layer, or ahard mask material such as SiO₂, followed by a selective RIE or anothersuitable etch technique may be employed to pattern the nitride layer 106in FIG. 18 as shown. More specifically, a region (e.g., rectangularregion) may be removed from the center of the nitride layer 106 therebyexposing a portion of the SOI layer 102.

FIGS. 20A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 20A-C, RIE or another suitable method may be employed to etchthe exposed portion of the SOI layer 102 selective to nitride and oxide.In this manner, the exposed portion of the SOI layer 102 may be removedwithout removing the nitride layer 106, and/or the buried oxide (BOX)layer 104. Consequently, one or more sidewalls 2000 of the SOI layer 102may be exposed. An exposed sidewall 2000 may serve as a first side 2002of a subsequently formed fin (2600 in FIG. 26B) of the FinFET beingmanufactured. While the first side 2002 of the fin is formed, anultimate second side of the fin is included in the SOI layer 102 andsupported thereby. In this manner, a perimeter of the opening formed byremoval of the nitride layer may define, in part, a location or one ormore fins subsequently formed during the second exemplary method. Itshould be noted from the cross-sectional front views, that the secondexemplary method may form two FinFETs in the substrate 1800 (e.g., afirst FinFET on the left side of the cross-sectional front views and asecond FinFET on the right side of the cross-sectional front views). Forease of description, when convenient, only the FinFET manufactured onthe left side of the cross-sectional front views may be referenced.

FIGS. 21A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a first gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.With reference to FIGS. 21A-C, thermal oxidation, thermal nitridationand/or conformal deposition, or another suitable method may be employedto form a first dielectric 2100 on the exposed sidewall 2000 of the SOIlayer 102. A portion 2102 (shown in phantom) of the SOI layer 102 onwhich the first gate dielectric 2100 is formed may subsequently beformed into a fin (2600 in FIG. 26B). In this manner, the first gatedielectric 2100 may be formed on a first side 2002 of the fin. The firstgate dielectric 2100 may include at least one of a silicon oxide,silicon oxynitride, silicon nitride and high-k dielectric (e.g.,silicon-hafnium-oxynitride). However, the first gate dielectric 2100 mayinclude a larger or smaller number of and/or different gate insulatormaterials. The electrical thickness of the first gate dielectric 2100may be about 1 nm to about 6 nm (although a larger or smaller thicknessmay be employed).

FIGS. 22A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a first gate conductor is formed on thesubstrate and an oxide layer is formed on the gate conductor inaccordance with an embodiment of the present invention. With referenceto FIGS. 22A-C, CVD or another suitable method may be employed todeposit a first gate conductor layer 2200 on a top surface of thesubstrate 1800. Thereafter, CMP or another suitable method may beemployed to planarize the first gate conductor layer 2200 to a topsurface 2202 of the nitride layer 106. The first gate conductor mayinclude at least one of polysilicon (e.g., doped or undoped), a silicide(e.g., nickel silicide or tungsten silicide) and/or a refractorymaterial (e.g., tungsten). However, the first gate conductor may includea larger or smaller number of and/or different materials. The first gateconductor material may determine the work function of a first gatesubsequently coupled thereto and a threshold voltage V_(t) associatedwith the first gate.

RIE or another suitable method may be employed to recess the first gateconductor layer 2200 below a top surface 2202 of the nitride layer 106.For example, the first gate conductor layer 2200 may be recessed about 5nm to about 50 nm below the top surface 2202 of the nitride layer 106(although the first gate conductor layer 2200 may be recessed a largeror smaller distance). CVD or another suitable method may be employed todeposit a layer 2204 of oxide on a top surface of the substrate 1800.CMP or another suitable method may be employed to planarize the oxidelayer 2204 to a top surface 2202 of the nitride layer 106. In thismanner, the oxide layer 2204 may serve as a protective cap for the firstgate conductor layer 2200.

FIGS. 23A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide regions 2300-2304 are formed in thenitride of the substrate 1800 in accordance with an embodiment of thepresent invention. With reference to FIGS. 23A-C, oxide regions2300-2304 may be formed by patterning openings onto the nitride layer106 using a patterning technique such as photolithography usingphotoresist and appropriate masking. For example, portions of thenitride layer 106 may be exposed through use of a mask employed duringthe patterning technique. Thereafter, RIE or another suitable method maybe employed to remove portions of the nitride layer 106 exposed throughthe openings selective to silicon. Therefore, the etching of exposednitride in the nitride layer 106 may stop at silicon of the SOI layer102.

Oxide (e.g., SiO₂) may be deposited on the substrate 1800 using CVD oranother suitable deposition method such that the oxide is deposited inthe regions 2300-2304. Thereafter, CMP or another suitable technique maybe employed to planarize a top surface of the substrate 1800 to a topsurface 2202 of the nitride layer 106. In this manner, the oxide regions2300-2304 may be formed. The oxide regions 2300-2304 may define regionsfor subsequently formed pads (e.g., contact pads) to contact a source ordrain diffusion region of the substrate 1800. For example, a first andsecond oxide region 2300, 2302 may define regions for subsequentlyformed pads to contact first and second drain diffusion regions (e.g.,regions of silicon beneath the first and second oxide regions 2300,2302), respectively, of the substrate 1800. Similarly, a third oxideregion 2304 may define a region for a subsequently formed pad to contacta source diffusion region (e.g., a region of silicon beneath the thirdoxide region 2304) of the substrate 1800. In this manner, damascenedregions may be formed which may serve as etch masks when subsequentlydefining one or more contact pads.

FIGS. 24A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which nitride is etched from the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 24A-C, RIE or another suitable method may be employed to etchnitride selective to oxide and silicon. In this manner, exposed portionsof the nitride layer (106 in FIGS. 23A-C) may be etched (e.g., down tothe SOI layer 102), and thereby removed from the substrate 1800.

FIGS. 25A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide spacers are formed on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 25A-C, CVD or another suitable technique may be employed todeposit (e.g., conformally) a layer of oxide over a top surface of thesubstrate 1800. In this manner, a layer of oxide may form on exposedportions of a top surface 2500 of the SOI layer 102, exposed portions ofa top surface 2502 of the oxide layer 2204 (e.g., protective cap),exposed portions of a top surface 2503 of the oxide regions 2300-2304exposed sidewalls 2504 of the first gate conductor 2200, exposedsidewalls 2506 of the oxide layer 2204 and/or exposed sidewalls 2508 ofthe oxide regions 2300-2304. Thereafter, RIE or another suitable etchingmethod may be employed to etch the oxide layer selective to nitride. Forexample, portions of the oxide layer deposited on the top surface 2500of the SOI layer 102, the top surface 2502 of the oxide layer 2204and/or top surface 2503 of the oxide regions 2300-2304 may be removed.In this manner, oxide spacers 2510 may be formed on sidewalls (e.g.,vertical sidewalls) of the first gate conductor 2200, exposed sidewalls2506 of the oxide layer 2204 and/or exposed sidewalls 2508 of the oxideregions 2300-2304.

The thickness of the deposited layer of oxide may determine a width ofthe oxide spacer, which may determine a width of one or more fins thatare subsequently formed. In one embodiment, the thickness of thedeposited layer of oxide, and therefore, the oxide spacers 2510 may beabout 2 nm to about 50 nm. However, a larger or smaller thickness may beemployed.

FIGS. 26A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which silicon is etched from the substrate inaccordance with an embodiment of the present invention. RIE or anothersuitable method may be employed to etch silicon selective to oxide. Inthis manner, exposed portions of the SOI layer 102 may be etched (e.g.,down to the BOX layer 104), and thereby removed from the substrate 1800.Consequently, a fin 2600 of the FinFET (e.g., a first FinFET) beingmanufactured may be formed. More specifically, the silicon etchingcauses one or more sidewalls 2602 of the SOI layer 102 to be exposed. Asidewall 2602 of the SOI layer may serve as a second side 2604 of thefin 2600. In this manner, the fin 2600 of the FinFET may be formed. Itshould be noted while the second side 2604 of the fin 2600 is formed,the first gate conductor layer 2200 and first dielectric layer 2100support the first side 2002 of the fin 2600. The width of the fin 2600may be defined by the oxide spacer 2510 overlying the fin 2600.Additionally, the silicon etching may form diffusion landing pad regions(e.g., rectangular regions) to which subsequently formed contacts maycouple. It should be noted that a fin 2606 of another FinFET (e.g., asecond FinFET) that may be manufactured may also be formed in this step.Doping similar to that described with reference to FIGS. 8A-C may now beemployed.

FIGS. 27A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a second gate dielectric is formed on thesubstrate in accordance with an embodiment of the present invention.With reference to FIGS. 27A-C, thermal oxidation, thermal nitridationand/or conformal deposition, or another suitable method may be employedto form a second dielectric 2700 on the sidewall 2602 of the SOI layer102. In this manner, the second gate dielectric 2700 may be formed onthe second side 2604 of the fin 2600. The second gate dielectric 2700may include at least one of a silicon oxide, silicon oxynitride, siliconnitride and high-k dielectric (e.g., silicon-hafnium-oxynitride).However, the second gate dielectric 2700 may include a larger or smallernumber of and/or different gate insulator materials. The electricalthickness of the second gate dielectric 2700 may be about 1 nm to about6 nm (although a larger or smaller thickness may be employed). In someembodiments, the second gate dielectric material and/or width may bedifferent than the first gate dielectric material and/or width,respectively (although the first and second gate dielectrics may be ofthe same material).

FIGS. 28A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a second gate conductor is formed on thesubstrate and planarized in accordance with an embodiment of the presentinvention. With reference to FIGS. 28A-C, CVD or another suitable methodmay be employed to deposit a second gate conductor layer 2800 on a topsurface of the substrate 1800. Thereafter, CMP or another suitablemethod may be employed to planarize the second gate conductor layer 2800to a top surface of the oxide layers (e.g., the oxide regions 2300-2304in FIG. 25A and the oxide layer 2204). FIGS. 29A-C illustrate respectivetop, cross-sectional front and cross-sectional side views of a step ofthe second exemplary method of forming a FinFET in which oxide and thesecond gate conductor are planarized in accordance with an embodiment ofthe present invention. With reference to FIGS. 29A-C, an over polish maybe employed to remove (e.g., planarize) portions of the second gateconductor layer 2800 atop the first gate conductor layer 2200 and toremove the oxide layer (e.g., oxide cap) (2204 in FIG. 28B) atop thefirst gate conductor layer 2200. Consequently, top portions of the oxidespacer 2510 may be planarized. The second gate conductor may include atleast one of polysilicon (e.g., doped or undoped), a silicide (e.g.,nickel silicide or tungsten silicide) and/or a refractory material(e.g., tungsten). However, the second gate conductor may include alarger or smaller number of and/or different materials. The second gateconductor material may determine the work function of a second gatesubsequently coupled thereto and a threshold voltage V_(t) associatedwith the second gate. In some embodiments, the second gate conductormaterial may be different than the first gate conductor material(although the first and second gate conductor materials may be thesame).

FIGS. 30A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which oxide above a fin is etched from the substratein accordance with an embodiment of the present invention. Withreference to FIGS. 30A-C, an etching mask 3000 may be formed on thesubstrate 1800. For example, a photoresist layer may be applied to thesubstrate 1800 and patterned to form the etching mask 3000. Thereafter,the etching mask 3000 may be employed with a suitable etching method toselectively etch an opening 3002 in an oxide spacer 2510 overlying a fin3004. The opening 3002 may enable subsequent access to the fin 3004, forexample, during patterning of the gate conductor layers 2200, 2800. Inthis manner, such fin 3004 may be selectively cut in what is known as atrimming operation.

FIGS. 31A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which a fin and portions of the first and secondgate conductors are etched from the substrate in accordance with anembodiment of the present invention. With reference to FIGS. 31A-C, ananisotropic etch such as RIE, a combination of an anisotropic and anisotropic etch selective to oxide and nitride, or another suitablemethod may be employed to pattern the first and second gate conductorlayers 2200, 2800 (e.g., selective to oxide) into a resulting region3100. Consequently, portions of the first and second gate dielectrics2100, 2700 may be exposed. Additionally, one or more portions of the fin(3004 in FIG. 30C) exposed by the opening (3002 in FIG. 30C) may also beremoved while the gate conductor layers 2200, 2800 are etched. Removingthe fin 3004 may cause portions of the gate dielectric layers 2100, 2700previously coupled to the fin 3004 to be left free standing. Therefore,such portions of the dielectric layers 2100, 2700 may fall off of thesubstrate 1800.

FIGS. 32A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which portions of the gate dielectrics are etchedfrom the substrate in accordance with an embodiment of the presentinvention. With reference to FIGS. 32A-C, exposed portions of the firstand second dielectric layers 2100, 2700 may be removed (e.g., stripped).Therefore, sidewalls 3200 of silicon beneath the oxide regions 2300-2304may be exposed. Gas phase doping, angled ion implantation or anothersuitable method for doping the silicon beneath the oxide regions2300-2304, which may subsequently form a source or drain diffusionregion in the FinFET, may be employed. In this manner, a source, drainor halo dopant may be introduced to the silicon beneath one or more ofthe oxide regions 2300-2304. Depending on the different types ofsemiconductor devices that are being manufactured, multiple maskingsteps may be employed during doping to provide desired doping effects tothe different device types. During doping of the silicon beneath theoxide regions 2300-2304, the oxide spacer 2510 overlying the fin 2600,which may serve as conducting channel, may prevent the channel frombecoming contaminated (e.g., by unwanted dopants).

FIGS. 33A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which an insulator is deposited on the substrate inaccordance with an embodiment of the present invention. With referenceto FIGS. 33A-C, CVD or another suitable method may be employed todeposit an insulator layer 3300, such as a planarizing glass (e.g.,phosphosilicate glass (PSG), borosilicate glass (BSG),borophosphosilicate glass (BPSG), etc.) on a top surface of thesubstrate 1800. Thereafter, the insulator layer 3300 may be planarized.In some embodiments, the insulator may be reflowed to planarizeinsulator layer 3300. Alternatively, CMP or another suitable method maybe employed to planarize the insulator layer 3300. Further, in contrastto the glass described above, in some embodiments, a spin on dielectricor the like may be employed.

FIGS. 34A-C illustrate respective top, cross-sectional front andcross-sectional side views of a step of the second exemplary method offorming a FinFET in which wiring is formed on a transistor formed in thesubstrate in accordance with an embodiment of the present invention.With reference to FIGS. 34A-C, masked anisotropic etching such as RIE oranother suitable method may be employed to etch one or more contact vias3400 through the insulator layer 3300 (e.g., to the first gate conductorlayer 2200, second gate conductor layer 2800, a diffusion region 3401(e.g., silicon beneath an oxide region 2300-2304)). Thereafter, contacts3402 may be formed. Further, metallurgy patterning or another suitablemethod may be employed to form wiring to one or more of a first gateconductor contact, second gate conductor contact, a source diffusionregion contact and/or a drain diffusion region contact. As stated, thesecond exemplary method may form two FinFETs in the substrate 1800(e.g., a first FinFET 3404 on the left side of the cross-sectional frontview and a second FinFET 3406 on the right side of the cross-sectionalfront view). In some embodiments, a metal bridge 3408 may be formedbetween gate conductors 2200, 2800 formed on opposing sides of the fin2600 of the first FinFET 3404. In this manner, the first FinFET 3404 mayoperate with the same voltage applied to opposing gates (e.g., a firstgate coupled to the first gate conductor 2200 and a second gate coupledto the second gate conductor 2800) of the first FinFET 3404 (e.g.,similar to operation of a conventional FinFET). In contrast, the wiringof the second FinFET 3406 may be such that opposing gates operateindependently. In this manner the present methods and apparatus mayprovide a “split-gate” FinFET. However, the wiring for the first and/orsecond FinFET 3404, 3406 may be different. As described above, throughuse of the second exemplary method a FinFET in accordance with anembodiment of the present invention may be formed.

Through use of the first or second exemplary methods, support (e.g., onone or more sides) to silicon which ultimately forms a fin may beprovided during (e.g., throughout) manufacturing. In this manner, damageto a fin while manufacturing a FinFET may be reduced and/or eliminated,and therefore, a semiconductor device manufacturing yield may beimproved.

Further, in contrast to conventional methods, a structure of a FinFETresulting from the present methods is not limited. For example, a FinFETin accordance with the present methods and apparatus may include a firstgate conductor of a first material, which has a first work function,coupled to a first gate of the FinFET, and a second gate conductor of asecond, different material, which has a different work function, coupledto a second gate of the FinFET. Additionally or alternatively, a FinFETin accordance with the present methods and apparatus may include a firstgate dielectric of a first material coupled to a first side of a fin ofthe FinFET and a second gate dielectric of a different (e.g., second)material coupled to a second side of the fin. Alternatively oradditionally, a FinFET in accordance with the present methods andapparatus may include a first gate dielectric of a first width coupledto a first side of a fin of the FinFET and a second gate dielectric of adifferent (e.g., second) width coupled to a second side of the fin.

FIG. 35 illustrates a simulated relationship 3500 between drain currentand voltages of first and second gates of a FinFET 1704, 1706, 3404,3406 manufactured in accordance with an embodiment of the presentinvention. With reference to FIG. 35, the FinFET 1704, 1706, 3404, 3406(e.g., split-gate FinFET) may be useful for NOR gate logic. Thesimulation (e.g., Finite-Element Device Analysis (FIELDAY) simulation)is performed on a FinFET including a mid-gap work function gateconductor material, such as tungsten, WSi₂, NSi₂, etc. Further, theFinFET includes a 2 nm equivalent oxide thickness gate dielectric onboth sidewalls of a fin in the FinFET. Additionally, uniform p-typedoping of 1×10¹⁶ cm⁻³ is employed to create the fin. Therefore, bulkcharge contributions to a threshold voltage (V_(t)) may be negligible.In the simulated relationship 3500 between electrical characteristicssuch as drain current (Id) and gate voltages (Vg1, Vg2) of the FinFET1704, 1706, 3404, 3406, physical conditions and drain to source voltage(Vds) are shown in the legend 3504. For a first curve 3506, Vg1 (e.g., aleft gate voltage) and Vg2 (e.g., a right gate voltage) are ramped from0 to 1.0 V simultaneously (e.g., opposing gates of the FinFET are tiedtogether). In contrast, for a second curve 3508, Vg2 is held constant at0 V, while Vg1 is ramped from 0 to 1.0 V. The two distinct operatingmodes illustrated by the first and second curves 3506-3508,respectively, form the basis of compact logic structures usingsplit-gate FinFETs in accordance with an embodiment of the presentinvention. Although threshold voltages may appear high for logicapplications including gate conductors having a work gate function(e.g., mid-bandgap) of the present simulation, a lower and/or anoptimized Vt may be obtained by employing gate conductor work functionengineering to yield a desired work function (e.g., a more n-type gateconductor work function).

FIG. 36 illustrates first exemplary contours 3600 of constant electronconcentration in a plane cut through the channel of a FinFETmanufactured in accordance with an embodiment of the present invention.More specifically, with reference to FIG. 36, the plane may cut througha channel normal to a direction of a source-drain current of ann-channel FinFET in accordance with an embodiment of the presentinvention. The first exemplary contours 3600 indicate electronconcentration is substantial throughout a fin of the FinFET, whichcorresponds to volume inversion. Such contours 3600 may result whenvoltages (Vg1 and Vg2) applied to opposing gates of the FinFET,respectively, are biased at 0.8 V. It should be noted that in someembodiments electron concentration through the fin may vary by less thanone order of magnitude.

FIG. 37 illustrates second exemplary contours of constant electronconcentration in the plane cut through the channel of the FinFET of FIG.36 in accordance with an embodiment of the present invention. Withreference to FIG. 37, the second exemplary contours 3700 indicatechannel electrons are mainly confined to a left sidewall of the fin,which corresponds to surface inversion. Such contours may result when afirst gate (e.g., a left gate) of the FinFET is biased at 0.8 V while asecond gate (e.g., a right gate) of the FinFET is held at 0 V. It shouldbe noted that in some embodiments electron concentration through the finvaries by over six orders of magnitude, which may result in a muchlarger sub-Vt swing.

FIG. 38 illustrates a layout 3800 of conventional MOSFETs on a substrateto form NOR logic. With reference to FIG. 38, a layout 3800 of atwo-input NOR gate using conventional SOI CMOS transistors is shown. Thelayout 3800 requires 342 F² of substrate area, where F represents aminimum lithographic feature size.

In contrast, FIG. 39 illustrates a layout 3900 of FinFETs on a substrateto form NOR logic in accordance with an embodiment of the presentinvention. With reference to FIG. 39, a layout of a two-input NOR gateusing split-gate FinFETs 1704, 1706, 3404, 3406 is shown. In contrast tothe layout 3800 of conventional MOSFETs, the layout 3900 of FinFETsrequires 112 F² of substrate area. Therefore, the FinFETs in accordancewith an embodiment of the present invention may use chip real estatemore efficiently than conventional transistors.

The foregoing description discloses only exemplary embodiments of theinvention. Modifications of the above disclosed apparatus and methodswhich fall within the scope of the invention will be readily apparent tothose of ordinary skill in the art. For instance, the present methodsand apparatus may provide advantages such as (1) allowing independentwork functions for opposing gates of a FinFET by using differentopposing gate conductor materials (e.g., polysilicon and metal onrespective opposing sides, polysilicon and silicide on respectiveopposing sides, metal and silicide on respective opposing sides, etc);(2) allowing for independent gate dielectric materials and/orthicknesses on opposing sides of a FinFET fin; (3) allowing selectivebridging of opposing gates of a FinFET, if tied gate operation isdesired; (4) allowing for a gate-bridging conductor which is borderless(e.g., does not directly contact the gate conductors) to the cross thefin and couple opposing gates of a FinFET; (5) providing a robustprocess which protects the structural integrity of a FinFET fin, whichmay be narrow and/or have a high aspect ratio, through all processsteps, thereby minimizing process-induced damage; (6) employing“split-gate” transistors in a NOR circuit to reduce required chip realestate; and/or (7) reducing and/or eliminating diffusion underlapproblems toward a bottom of a FinFET fin. Further, the present methodsand apparatus may enable gate doping on opposing sides of a fin toremain separated. Additionally, the present methods and apparatus may beintegrated with conventional planar CMOS technology.

It should be noted the present invention also provides advantagesconventionally provided by FinFET technology over planar CMOStechnology, such as (1) a near ideal sub-Vt slope; (2) greatly reducedshort-channel effects; (3) a greatly reduced floating-body parasiticbipolar effect due to inherent fully-depleted operation; (4) improved Vtmatching due to negligible ionized impurity bulk charge; (5) a highcurrent drive due to volume inversion and height of fin; and/or (6) arelaxed need for gate dielectric scaling. Such advantages are known toone of skill in the art, and therefore, are not described in detailherein.

Accordingly, while the present invention has been disclosed inconnection with exemplary embodiments thereof, it should be understoodthat other embodiments may fall within the spirit and scope of theinvention, as defined by the following claims.

1. A method of semiconductor device manufacturing, comprising: forming afirst side of a fin of a fin field effect transistor (FinFET);processing the first side of the fin; and forming a second side of thefin while supporting the first side of the fin.
 2. The method of claim 1wherein forming the first side of the fin of the FinFET includes formingthe first side of the fin of the FinFET while supporting an eventualsecond side of the fin.
 3. The method of claim 1 wherein processing thefirst side of the fin includes forming a dielectric of a first materialon the first side of the fin.
 4. The method of claim 3 whereinprocessing the first side of the fin includes forming a gate conductorof a first material on the first side of the fin.
 5. The method of claim1 further comprising processing the second side of the fin.
 6. Themethod of claim 5: wherein processing the first side of the finincludes: forming a dielectric of a first material on the first side ofthe fin; and forming a gate conductor of a first material on the firstside of the fin; and wherein processing the second side of the finincludes forming a dielectric of a second material on the second side ofthe fin.
 7. The method of claim 6 wherein processing the second side ofthe fin further includes forming a gate conductor of a second materialon the second side of the fin.